The present invention relates to a flip-flop circuit and more particularly a flip-flop circuit including four logical gates and single input and output lines.
A master-slave type flip-flop circuit have been known for binary counters or frequency-dividing circuits. This type flip-flop is shown in FIG. 1, including a first R-S FF (flip-flop) 1 having gates G.sub.1 to G.sub.4 and a second R-S FF having gates G.sub.5 to G.sub.8. Clock pulses CP for control is applied to the first FF circuit 1 and clock pulses CP for control to the second FF circuit 2. Output signals Q.sub.2 and Q.sub.2 are taken from the gates G.sub.8 and G.sub.7, respectively. When the clock pulses CP and CP are used as input signals, the CP is at high level against low level of the CP and at low level against high level of the CP. In the first step, when the output Q.sub.2 is at high level (V.sub.H), input control gates G.sub.1 and G.sub.2 are enabled when the CP becomes high in level and the output Q.sub.1 of the first FF circuit 1 becomes V.sub.H. In the step 2, the CP becomes low (V.sub.L) in level so that the control gates G.sub.1 and G.sub.2 are disabled. On the other hand, the CP becomes V.sub.H to enable the input control gates G.sub.5 and G.sub.6 of the FF circuit 2. Accordingly, the output of the FF circuit 2 is inversed and thus its output Q.sub.2 becomes V.sub.L. In the step 3, the CP becomes V.sub.L to disable the control gates G.sub.5 and G.sub.6 . In this manner, the clock pulses CP and CP become alternately V.sub.H and V.sub.L and the state of V.sub.H is alternately switched between the flip-flop circuits 1 and 2. That is, the level of the output Q.sub.2 becomes V.sub.H one time every two times of V.sub.H states of the CP.
The master-slave type flip-flop circuit needs eight gates and two input and output lines, as shown. This makes it difficult to fabricate a number of flip-flop circuits by using high density integrated circuits. It must be avoided, further, that both waveforms of the CP and CP are concurrently V.sub.H in any time period. This restricts the waveform of the clock pulse.
Accordingly, the primary object of the invention is to provide a flip-flop circuit in which the much the same function as of the FIG. 1 flip-flop may be attained by using four logical gates and single input and output lines.